This invention relates to analog-to-digital converters and to a comparator circuit useful in a simplified parallel analog-to-digital converter.
A conventional parallel analog-to-digital (A/D) converter compares an analog input signal to each input from a set of discrete voltage levels which define voltage intervals. The converter produces a digital output indicative of the voltage interval into which the analog input signal falls. A separate voltage comparator is associated with each reference level to compare the analog input to that level. Hence, for an n bit digital code which can indicate any of 2.sup.n voltage intervals defined by 2.sup.n -1 quantum levels, 2.sup.n -1 comparators are required. The reference inputs to the comparators are generally taken from a string of 2.sup.n resistors of equal resistance values arranged in series across a reference voltage. The outputs of the 2.sup.n -1 comparators drive a logic tree to decode the comparator outputs into n bits. Using the conventional circuits, a three bit converter requires seven comparators and a seven-input logic network; and a four bit converter requires fifteen comparators and a fifteen-input logic network.
An object of this invention is to provide an improved A/D converter.
A more specific object of this invention is to provide an A/D converter of the parallel type, and which uses only a relatively small number of comparators to produce an output code.